The parallel expander¶
The parallel expander is mapped add address 0x44 on the configuration-\(\text{I}^2 \text{C}\) bus. Each bit controls one of the functions shown below:
Bit(s): |
Function: |
|---|---|
1..0 |
RS232 selection |
3..2 |
Touch screen/LCD panel selection |
4 |
SD-card reader control |
5 |
Led array control |
6 |
User-CPU reset |
7 |
ZMOD control |
Note
By reset all the bits of the parallel expander are set to input mode. The parallel expander provides pull-down resisters, such that all the bits correspond to 0.
The data-sheets of the parallel expander can be found here.
RS232 selection¶
The USB-hub provides a UART-device that can be connected to different sources/targets on the leguan board. Bits 1..0 of the parallel expander control the connection as shown below:
Bits 1..0 |
Source/target |
|---|---|
00 |
Blackmagic probe |
01 |
User-CPU |
10 |
Firmware-CPU |
11 |
FPGA |
Touch screen/LCD panel selection¶
Bits 3..2 of the parallel expander control to which device the LCD-panel and touch-screen is connected. The configuration is shown below:
Bits 3..2 |
Source/target |
|---|---|
0- |
Firmware CPU |
10 |
FPGA |
11 |
User CPU |
Important
When the board is put in SOC-mode the LCD-panel and touch-screen need to be connected to the User CPU and the FPGA must not drive these signals!
SD-card reader control¶
Bit 4 of the parallel expander can enable (1) or disable (0) the integrated SD-card reader.
Important
The SD-card reader should only be enabled in menu-mode. In the other modes the signals of the sd-card are connected in parallel to both the FPGA and the user-CPU. Furthermore, in SOC-mode the FPGA should not drive these signals.
Led array control¶
Bit 5 of the parallel expander enables (1) or disables (0) the RGB-led-array and the seven-segment displays of the leguan board.
Note
This feature is provided to reduce the energy consumption of the leguan board and is for the moment not used. The firmware has to write a 1 to this bit in all situations.
User-CPU reset¶
Bit 6 of the parallel expander is used to keep the user-cpu in reset state (1) or to let the user-cpu run (0).
Note
When the user-cpu is in reset state all it’s pins are detached from the shared bus between the user-cpu and the FPGA, letting the FPGA take control of this bus.
When the user-cpu is in reset also the Segger JLINK/Blackmagic probe are kept in reset and are not available.
Important
The user-cpu should be held in reset in all modes except from the CPU-*-mode and SOC-*-mode!
The segger JLINK is very sensible to a fast reset change. Therefore, after board-reset, the firmware should wait > 0.5s before putting the User CPU in reset.
ZMOD control¶
Bit 7 of the parallel expander enables (1) or disables (0) the ZMOD connectors. See for more details the ZMOD control section.