Clock sources

The leguan board has two clock oscillators connected to the FPGA. Also two pins of the extended PMOD connector are connected to clock inputs. Finally the user-CPU provides two clock sources.

25 MHz clock source

The 25 MHz clock oscillator is connected to PIN_B11 of the FPGA. Below you find the snippets on how to use this clock source in your toplevel.

74.25 MHz clock source

The 74.25 MHz clock oscillator is connected to PIN_T22 of the FPGA. Below you find the snippets on how to use this clock source in your toplevel.

extended PMOD clock sources

The pins 7 and 8 of the extended PMOD connector can be used as clock inputs or as normal inputs. Pin 7 is connected to PIN_B12 of the FPGA, and pin 8 is connected to PIN_A12. Below you find the snippets on how to use these clock sources in your toplevel.

Important

These two pins cannot be used as an output, as they are connected to clock-input-pins of the FPGA.

user-CPU clock sources

The user-CPU provides a clock source of 216 MHz connected to PIN_G21 of the FPGA. Furthermore, it provides a 108 MHz clock source connected to PIN_G22 of the FPGA. Below you find the snippets on how to use these clock sources in your toplevel.

Important

As these clock sources are generated by the internal PLL of the user-CPU they might not be completely exact and/or jitter.

Using the clock sources

In this section you find a VHDL top-level entity and the corresponding tcl-files that you can use to use one/multiple of the above described clock sources.

Important

Although VHDL is case-insensitive, the tcl-files are not. Meaning that the port-names in the top-level entity need to be copied exactly in the tcl-files.

An example for a VHDL top-level entity is shown below:

library ieee;
use ieee.std_logic_1164.all;

entity leguanToplevel is
  port ( clock1  : in  std_logic;
         Clock2  : in  std_logic );
end leguanToplevel;

To connect clock1 to the 25 MHz clock source and Clock2 to the 216 MHz user-CPU provided clock, following tcl-script can be used:

set_location_assignment PIN_B11 -to clock1
set_location_assignment PIN_G21 -to Clock2

set_global_assignment -name SDC_FILE clocks.sdc

Note

1. The case-sensitivity of the tcl-files.

2. The statement set_global_assignment -name SDC_FILE clocks.sdc which includes the file clocks.sdc that contains the timing constraints.

Hint

To activate the assignments, following steps need to be taken in quartus:

1. Go to Tools->Tcl scripts....

2. Add the tcl script to your project by pressing the Button Add to Project....

3. Highlight the tcl script by clicking on it in the Libraries: window.

4. Press the Run button.

Now the final step to perform is to create the clocks.sdc file. This file is used by quartus to constraint the clocks to the correct values and, hence, give you the information if your system can run at this frequency. For the given example following clocks.sdc file can be used:

set_time_unit ns
set_decimal_places 3
create_clock -period 40.0 -waveform { 0 20.0 } clock1 -name contraint1
create_clock -period 4.629 -waveform { 0 2.314 } Clock2 -name constraint2

Important

This file needs to be put in the project directory (the one you specified when you created the project)! Quartus will automatically read this file when doing the Synthesis and P&R tasks, so no further actions from you are required.

Summary

Below a table with all required information for each clock source:

Clock source:	FPGA pin:	-period	-waveform
25 MHz	PIN_B11	40.0	{ 0 20.0 }
74.25 MHz	PIN_T22	13.468	{ 0 6.734 }
extended PMOD pin 7	PIN_B12	-	-
extended PMOD pin 8	PIN_A12	-	-
216 MHz	PIN_G21	4.629	{ 0 2.314 }
108 MHz	PIN_G22	9.259	{ 0 4.629 }